Understanding PCB Stackup: Materials and Layer Configuration
In PCBs or printed circuit boards, stackup design must address three concerns—controlled impedance, crosstalk, and interplane capacitance. While fabricators have some control over achieving the right impedance in a stackup, they cannot account for the other two. The design engineer is responsible for them, primarily, as the designer alone knows the requirements and the method of control necessary. Here, Rush PCB Inc is offering the necessary counseling on the process of setting up PCB stackups so the board can meet the necessary concerns.
Importance of PCB Layer Configuration
Some logic components in PCBs can be so fast that they produce harmful reflections. To prevent such reflections, it is necessary for the circuit to transmit high-speed signals along paths with a predetermined impedance. This requires PCBs to have controlled impedance along high-speed tracks. Fabricators can get the desired impedance by using special material for the substrates and controlling their thickness.
With two traces on a PCB running parallel for some distance, it is easy for high-speed signals on one trace to electromagnetically couple into the other, disturbing the signal quality in the latter trace. Designers avoid such crosstalk between traces by:
- Increasing the gap between the two traces, if they are on the same layer
- Inserting a ground/power plane between the two traces, if they are on adjacent layers
- Routing the traces so that they are perpendicular to each other
All the above are purely design related, and there is no contribution from the fabricator.
With the rise in signal speeds, especially above 100MHz, lack of capacitance causes an increase in failure to meet EMI requirements. Placing discrete capacitors on power rails fails to solve the problem as their mounting inductance is high. Designers provide buried capacitance or interplace capacitance by placing power and ground planes very close to each other. Typically, the distance between the two is less than 3 mils.
Importance of PCB Materials
PCBs often use differential pair traces to carry high-speed signals from the transmitter to the receiver. However, misalignment of the two sides of the differential pair traces or skew can attenuate the signal. Moreover, lossy materials of the laminate and prepreg often induces enough attenuation to destroy the signal before it reaches its destination. Designers must use low-loss laminates that do not cause signal attenuation.
Understanding PCB Stackup and Materials
The design engineer must take charge of the design to mitigate the above issues. To be successful, they require a thorough understanding of the fabrication process of the PCB and the materials used therein. This allows them to meet the above constraints—controlled impedance, crosstalk, interplane capacitance, skew, and signal loss.
For making the best decisions when designing a PCB stackup, it is helpful to understand the manufacturing process of printed circuit boards. While manufacturers use a number of methods for fabricating multilayer PCBs, foil lamination is the most common and economical among them.
For instance, a typical six-layer PCB has three basic components in its stackup:
- Copper Foil
After laminating and drilling the stackup, the outer layers of a PCB are always solid sheets of copper. Copper provides a path for the plating current with which the manufacturer plates copper in the drilled holes for component leads and vias.
Prepreg is the woven fiberglass cloth typically coated with a resin system. The resin depends on the particular design. It is only partly cured and serves as the adhesive when the fabricator laminates the stackup.
The laminate has the same resin/glass material as the prepreg. The laminate also has a layer of copper foil on each side bonded to the laminate. The press that bonds the copper foil to the laminate also cures the resin, so that the composition forms the laminate as a rigid material. The fabricator will etch the plane layers and inner signal paths on this laminate, two at a time.
The fabricator always forms the layers in pairs. For reasons of manufacturability, fabricators always design the stackup with even multiples of layers. The fabricator can use other forms of lamination for the buildup that involve multiple lamination cycles along with blind and buried vias. The cost of the board depends on the manufacturing processes the fabricator has used.
While manufacturing a multilayer PCB, one of the main considerations is achieving tight control over the impedance. The fabricator exercises this control in three ways—etching and plating the proper width of traces on the outer layers, etching the traces for the inner layers, and maintaining a specified thickness during the lamination cycle.
Etching is the process of removing unwanted copper between the traces, and affects the impedance of the traces depending on their width and spacing. Typically, the fabricator places an etch resist on all the copper circuits that must remain. This allows the etching solution to remove the bare copper. However, this also etches the copper sideways, resulting in the trace being wider at the bottom than at the top, forming a trapezoidal cross-section. The situation aggravates when the copper thickness is high, and the error grows. Therefore, for a good control over the impedance, a thinner copper layer is preferable. Fabricators, therefore, prefer to use ½ ounce copper layers for inner signal layers.
Fabricators plate up the copper layers on the outer layers first, for depositing copper in the holes. Later, they etch away the unwanted copper to form the signal traces. As the copper in the outer layers is thicker, great care is necessary to adhere to the specified tolerance. Therefore, fabricators use controled impedance only for signals in inner layers.
When laminating, the resin contained in the prepreg melts and flows, filling the voids in adjacent copper layers. The applied pressure during lamination squeezes the excess prepreg resin out from the edges of the board, causing the prepreg layers to thin down.
The distance between the trace layer and its nearest plane is the most important dimension for controlling the accuracy of the impedance. Designers prefer to match signal layers over plane layers across a laminate. The use of a lamination between two layers guarantees the accuracy of separation.
For a laminate system, its dielectric constant or Dk is important. The dielectric constant directly affects the parasitic capacitance of the laminate. In a transmission line formed by a copper trace, copper plane, and laminate, the impedance of the transmission line depends directly on the parasitic capacitance formed between the plane layer and the trace.
The dielectric constant inversely affects the impedance. This is because the parasitic capacitance increases with a higher dielectric constant. Therefore, an accurate knowledge of the types of laminates available is essential to fabricate PCBs with specific controlled impedance.
Manufacturers offer several types of laminates. Fabricators select laminate systems that are readily available in the region where they will make the PCBs. Most often, the data sheet for a laminate provided by the industry only conforms to an IPC standard. It has electrical information for typical loss tangent and dielectric constant measured at 1 MHz. However, both these quantities vary with frequency and the ratio of glass to resin. But for a reliable impedance calculation, the dielectric constant that the fabricator must use is for frequencies about 2 GHz. Fortunately, this laminate manufacturers furnish this information.
Arranging the Layers
The designer must determine the number of power planes and signal layers, arranging them such that the design complies with the signal integrity rules and power delivery needs. For proper interplane capacitance, the designer must space the ground and power planes close to each other. This may require a trade-off between routing signal on layers and the interplane capacitance for a multilayer PCB.
For instance, a stackup with only one pair of planes closely spaced may be good for routing space, but it is not very good for power delivery when there is need for interplane capacitance. On the other hand, two sets of plane pairs is good for providing interplane capacitance, but reduces the routing space substantially.
Controlled impedance PCBs that have two signal layers between a pair of planes, it is not possible to use a flooded ground layer or a full copper layer, as the full copper layer can alter the impedance of traces in adjacent layers.
According to Rush PCB Inc, the final cost of a printed circuit board depends on several factors that include the number of layers, requirements of plating, and the operations to create all the holes. Adding multiple laminations steps with number of layers also increases the cost. For a given number of layers, employing build-up technology and adding bind vias will push up the cost rapidly.