PCB Design Strategies for EMI/EMC Compliance
The role of PCB designers is an important one as far as the two areas of EMI and EMC are concerned. They must ensure laying out the design such that it generates noise below the regulatory limits. Many designs may be perfectly functional, yet unable to pass the regulatory standards because the designer has followed particular practices in the layout. The PCB designer must then modify the layout of the PCB to allow it to pass the regulatory standards.
As it is expensive to make repeated rounds of redesigns, prototype spins, and EMI/EMC compliance testing, designers are advised to follow simple steps to enable them to reduce the occurrence of excessive EMI/EMC in the layout. Some factors contributing to EMI/EMC may happen at the circuit level, and front-end engineers must address them during schematic capture. However, even when a circuit design is perfect, if its layout is not engineered properly, it can fail at EMI/EMC testing.
Any electronic design intended for high-volume market levels must have low noise emissions while operating. It is possible to have emissions being conducted away from the device through cables or radiated away from the device as RF emissions. Both types of emissions have their limitations which the regulatory authorities and industry standards groups specify. EMC compliance also encompasses ESD and the ability of electronic devices to withstand incoming transients. Broad areas and types of tests performed for new products are:
- Radiated Emissions
- Radiated Immunity
- Conducted Emissions
- Conducted Immunity
- Electrostatic Discharge
- Electromagnetic Field
- Power Frequency Magnetic Field
- Voltage Dips and Interruptions
- Surge Immunity
All the above tests are only necessary for some equipment. For instance, the test on voltage dips and interruptions is not necessary for a device operating on battery power.
However, passing these tests is a regulatory matter. Many companies specialize in testing electronic equipment to make sure they comply with the regulatory requirements. As these tests are expensive, companies cannot afford to repeatedly test and must learn to spot potential problems before sending a design for testing.
Designing for EMI/EMC Compliance
Design engineers need to change their thought processes a bit to ensure EMI/EMC compliance. Basically, they must be able to match the noise in the PCB layout to the radiator that the EMI/EMC standards define and locate areas from where noise is likely to couple into a cable connected to the system. The earlier in the design they are able to spot potential EMI/EMC problems, the quicker the solutions will be available.
PCB Layout and Routing
The noise characteristic of a circuit depends to a large extent on its layout and routing. Even when the designer has optimally laid out a design to reduce noise, there can be parasitic coupling between sources of noise and circuits, or from circuits radiated to free space. Although difficult to summarize such issues of parasitic coupling, there are two broad characteristics that potentially create them:
Loop Inductance — Possible to reduce with tighter coupling by using shorter paths between components, thereby reducing radiation.
Coupling Capacitance — Possible to reduce with better coupling to ground between circuits.
Cable entries and exits often have excessive conducted emissions. This is possible even when the PCB layout and routing are optimal. In such cases, adding a common-mode filter circuit or choke helps to a large extent. The coupling could be because of the floating enclosure or improper ground. Common-mode chokes are an easy fix, helping to ensure conducted emissions compliance, provided functionality is not affected by the noise problem.
Stackup and EMI/EMC
Bad stackup design is often the root cause of common radiated emission problems, as the stackup fails to suppress noise generated by components. It may also be due to bad routing practices leading to excessive radiated emissions. Bad stackups are also the root cause of conducted emissions. This is primarily due to system-level grounding issues creating excessive common-mode noise.
Within a stackup, a simple method that helps to solve most EMI problems is the judicial placement of a ground plane. The ground plane not only ensures low noise, it also maintains proper impedance for high-speed and RF signals, while reducing capacitive/inductive coupling.
Using a ground layer between signal layers introduces shielding between signal groups that would otherwise have resulted in cross-talk. The ground layer also reduces radiated emissions from the tracks, while easing the task of routing effective return paths during signal transitions. This strategy of using a ground plane helps to solve a myriad of EMI/EMC problems that signal propagations create.
It is possible to use a modular approach for building electronic products, provided the modules have individually passed EMI/EMC testing. For instance, using the FCC’s Modular Certification, it is possible to use pre-certified wireless modules to build a final product. This can eliminate RF testing from the certification process of the device as the modules are already certified in their individual radio bands.
However, the above certification does not eliminate the requirement for compliance to other emission tests for the product. It only reduces the risk of failures while helping to speed up the time to market.
Additional enclosure-level or board-level shielding should not be necessary simply to pass the EMC testing, provided the PCB layout has been done right. The basic reason is shielding adds to the component and assembly costs. Although negligible for a prototype, the costs can add up to a substantial amount for high volumes. Therefore, it is better to avoid shielding to not only simplify the design but lower the costs as well.
However, there can be exceptions. Adding a shielding to an existing design that must be taken to market quickly, can offer the lowest risk and cost moving forward. Sometimes, the board may have a noisy component generating too much noise that no amount of stackup, layout, and/or routing can mask—a shield may be the only solution. Shielding may be useful for EMC testing in cases of:
- At the component level — using through-hole or SMD shielding cans
- At the board level — using edge plating, conformal coatings
- At the enclosure level — using ferrite plates, absorbing elastomers, gaskets, metalized enclosures, and metallic tapes for sealing mating surfaces.
Although shielding can be a tempting solution for fixing pesky EMI problems, following proper design guidelines can get rid of most of the EMI/EMC issues.
PCB Design Guidelines for EMI/EMC Reduction
It is possible to design a board with low or near-zero EMI. With proper design guidelines, designers can make sure they do not create antennas that can emit electromagnetic energy. These best practices help to reduce the length and area of potential signal return paths, thereby reducing unwanted EM emissions. Proper multi-level stackup can play a critical role in digital and high-power applications. Appropriately routing signal traces from components to the processor can significantly reduce the return path, preventing common-mode signal generation. Some general PCB design rules for reducing EMI/EMC are as follows:
A PCB typically has many conductive paths, called traces, carrying signals and currents between components. Any cross or bend in the path of these traces creates a radiating antenna for EM radiations. Preferably, all traces must be laid out straight, and if it is necessary to bend them, use a smooth curvature, or at worst, a 45° turn—but avoid a 90° turn at all costs.
A certain level of separation between adjacent traces is necessary to avoid cross-talk. As a thumb rule, it is preferable to use a separation of 3W, where W is the trace width. However, the separation may have to be greater in case of higher signal strength or frequency. Differential traces do not have to follow trace separation. Rather, the closer they are, the better.
All multi-layer PCBs require the use of vias for signal routing. However, each via introduces capacitance and inductance effects. Therefore, it is highly desirable to route a critical signal on a single layer as far as possible, avoiding the introduction of vias. The parasitic inductance and capacitance introduced by a via can cause an impedance mismatch between the via and its trace, thereby creating reflections and affecting signal integrity.
If it is not possible to avoid introducing vias, ensure placing ground vias close to signal vias, thereby ensuring that signals have a connected ground reference. This reduces changes in the characteristic impedance value of the via and reduces reflections. For differential signals, place the same number of vias in both traces, if not possible to avoid them.
It is preferable to have no stubs in high-frequency and sensitive traces. Like vias, stubs produce reflections and can add a fractional wavelength antenna to the circuit.
Guard and Shunt Traces
Clock circuits need highly stable and noise-free supply rails. For this, designers use decoupling capacitors. In addition, the use of guard and shunt traces can protect clock lines for EM radiation coupling.
Ground Planes and Grids
Preferably use the entire ground plane as an unbroken layer. This allows the signal returns to face the least inductance value. Where a complete unbroken ground layer is not possible, designers often resort to using a ground grid. Here, the inductance depends on the spacing between the grid lines.
Short Return Paths
According to Faraday’s law, the return path of a signal creates a ground loop that radiates as an antenna. Therefore, the longer the return path, the stronger the radiation. A short return path, on the other hand, offers better EMI performance as it has a lower impedance. Longer return paths cause greater mutual coupling and result in cross-talk. One way to reduce ground loops is to connect device grounds directly to the ground plane.
By adding a ground track all around the edges of a PCB, it is possible to create a Faraday cage. For this, it is necessary to place the ground track on the edges of both the outer layers of a multilayer PCB and stitch them together using closely spaced vias. To be effective, there must be no routing of any signal beyond the boundary. The technique restricts all emissions/interference within the Faraday cage.
It is preferable to place low-speed circuits closer to the power plane while placing high-speed circuits closer to the ground plane.
Ground all Copper Fills
Copper fills and areas should preferably be connected to the ground, to prevent them from acting as antennas and causing EMI.
The arrangement of layers affects the EMC performance of a PCB. It is preferable to use an entire layer as a ground plane or a power plane in multi-layer boards. It is advisable to use signal layers sandwiched between ground and power layers, that is, use alternate signal and ground layers, while always keeping an even number of layers.
Separate Sensitive Circuits
For an EMI/EMC-friendly design, it is always preferable to group sensitive circuits according to the signals they are handling. These include digital circuits, analog circuits, high-speed circuits, low-speed circuits, and power circuits. Keeping signal tracks from each circuit group in their defined area is advised. If interconnection is necessary, using a filter helps.
Switching noise in power lines or traces connected to an IC can disturb its functioning. Likewise, a switching IC can contribute noise to the power line or traces. Decoupling capacitors helps curb the propagation of such switching noise. Placing the decoupling capacitor as close as possible to the IC is preferable while grounding the capacitor directly to the ground plane. Using power planes rather than power traces also helps reduce the propagation of switching noise.
For circuits carrying high-speed signals, impedance matching between the source and the destination is of utmost criticality. This is because unmatched impedance causes signal reflections and ringing. This further generates excess RF energy, which is likely to radiate or couple to other parts of the circuit. Designers must select the proper material for the PCB to control the impedance of traces while using special design techniques for laying and routing the trace.
The objective of compliance with EMI/EMC standards is to maintain compatibility between different electronic systems and enable a trouble-free operation. At Rush PCB Inc., we take infinite care to ensure signals on a PCB do not interfere, while traces, vias, and all board components work harmoniously in unison. Designing a PCB for EMI/EMC compliance prevents adding extra cost to the final product. Therefore, it is highly recommended to start early on in the design phase.