How Channel Operating Margin Helps High-Speed PCB Analysis
At Rush PCB, one of the requirements of designing high-speed electrical channels on a PCB is the evaluation of its performance. For instance, one may have high-speed data lines from the IC pins to the pluggable connector at the edge of the PCB, forming a channel. Note that several factors may affect the integrity of signals traveling along such high-speed data links:
- Dimensions of the track
- Dielectric material properties of the PCB
- Discontinuities between the track and component pads causing reflections
- Length and type of track used—strip line or microstrip
- Physical configuration of vias along the way
- Dependency of signal quality such as jitter on data pattern
- Temperature dependency.
Of the above, dimensions of the track along with the dielectric material properties of the PCB are more influentially prohibitive with increasing frequency. For instance, the frequency dependent dielectric constant of the PCB material governs the effective capacitance around the transmission lines.
As the electromagnetic wave travels through the dielectric, its velocity reduces proportional to the square root of the dielectric constant. That means as the dielectric constant increases, the velocity of the wave reduces. If the frequency of the wave increases, the effective dielectric constant of the various dielectric materials manufacturers use for PCBs also decreases. Therefore, the group velocity of an electrical signal depends on its frequency and this effect is called dispersion.
At Rush PCB, we realize that apart from the absorption of electrical energy by the dielectric, the skin effect of the conductor also contributes to the losses in transmission. The skin effect causes the current flow to remain confined to the surface of the conducting material, in this case, the copper traces. Increasing the width of the copper traces, that is, increasing the width of the transmission line, helps to mitigate the skin effect. However, as the signal frequency increases, dielectric losses increase faster than skin-effect losses do, and as a consequence, dielectric losses can be the dominant loss mechanism for very high data rate systems.
Therefore, for frequencies above 5 GHz, the combination of PCB material and trace dimensions becomes an important factor in finding the trade-off between low channel loss. In high-speed PCB design, low channel loss may be defined as low attenuation in maintaining signal levels well above thresholds of digital decisions, and minimizing standing wave effects or jitter through the proper amount of attenuation of unwanted reflections.
It is imperative to avoid discontinuities in the transmission line to transmit only a clean signal with proper voltage levels and well-defined edges. The type of tracks used, strip line or microstrip, both have their advantages and disadvantages when transmitting high-speed data.
For instance, impedance discontinuities in the data line may be caused by the presence of vias, leading to multiple electrical reflections. Presence of vias may be troublesome in achieving the required signal quality at frequencies above 1 GHz.
Engineers typically measure the channel performance parameters in the frequency domain according to Annex 698 of the IEE 802.3ap specification. However, this does not allow trade-offs between the various impairments of the channel.
For instance, a channel with low loss characteristics can tolerate higher cross talk or higher insertion loss deviation or both. However, the hard limits of the standard do not allow the system designer to make this trade-off, thereby leading to overdesign.
The specification also does not define constraints related to reference feed-forward equalization and reference equalization required for interoperability. For IC manufacturers this meant over-designing their chips to avoid possible failures. In some cases, their links would fail in the lab even when they met the limits of the frequency domain parameters. The reverse was also true, as links working properly on real hardware had failed their specification masks.
Accordingly, a new standard is operational, and this is the 100 Gigabit Ethernet Interface Standard, the IEEE 802.3bj (Annex 93), which includes the fundamentals of Channel Operating Margin.
Introducing Channel Operating Margin
More than 200 eminent manufacturers including Rush PCB use an emerging algorithm-based method, the Channel Operating Margin (COM), for ensuring compliance when designing high-speed PCBs, especially those working beyond 25 Gbit/sec and its associated areas such as SERDES.
At Rush PCB, we find compliance challenges becoming more complex when data rates increase beyond 3 Gbit/sec. Between 1 and 3 Gbit/sec, device speed related eye diagrams were adequate. Working with data rates between 3 and 8 Gbit/sec required some equalization to meet the requirements of the eye mask. Working around 10 Gbit/sec.
Going beyond 25 Gbit/sec and up to 28 Gbit/sec, bundling the above techniques along with COM allows an algorithmic analysis of the transmitter, the channel, and the receiver. At Rush PCB, we accommodate this framework using some minimum architectural designs for the transmitter and the receiver.
Engineers at Rush PCB break down the requirement into that of the driver, the channel, and the receiver. For us, the channel represents the traces on the PCB, and other structures such as vias.
Applying Channel Operating Margin
At Rush PCB, we run COM as a black box with a series of S-parameters as the base. For SERDES responsiveness, COM considers these along with other factors such as noise and jitter. COM outputs a figure of merit in dB. As a first pass, the designer must exceed a threshold value of 3 dB. If COM returns higher dB values, it means the design is that much more robust.
With the use of COM, Rush PCB has been able to make a complex task easier. Moreover, it benefits the design as the PCB does not have to be over-designed as earlier to achieve compliance to high-speed performance.
For Rush PCB, COM is flexible, easy, and efficient to use. Compared to full statistical simulators, COM makes several assumptions necessary to simplify the algorithm and improve its performance. It is an evolving package, and JCOM is addressing some of COM’s limitations and allow custom device packages to be used jointly with the COM algorithms.