All About ELIC for HDI PCBs

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Rush PCB Inc makes multilayer printed circuit boards containing many layers. With increasing demand for greater number of layers in PCBs, each layer is becoming thinner than ever before. We recommend PCB designers to use ELIC or Every Layer Interconnect technology for creating very thin, flexible PCBs with high functional density. Such advanced HDI boards typically feature multiple layers with stacked copper-filled microvias for enabling extremely complex interconnections.

Also known as any-layer HDI, ELIC HDI boards feature each layer containing its own laser-drilled and copper-filled microvias. ELIC boards make use of only copper filled and stacked microvias for making connections between each layer. Completing the stackup of layers allows each layer to connect to any other layer in the PCB. Achieving a substantial increase in the level of flexibility, the ELIC technology allows designers to maximize the interconnect density of the board.


ELIC for HDI Routing

Designers and manufacturers route HDI PCBs conforming to several PCB stackup standards as guided by IPC-2226. Following the standard helps them to trace routing for fine-pitch components like BGA or Ball Grid Arrays. Designers typically use standard HDI PCB construction stackup with buried vias, and through-hole vias linking all layers. For accessing inner layers of the PCB, designers additionally use blind/buried microvias to create BGA breakouts, and skip vias on the surface layers of the board.

With PCBs becoming increasingly thinner and containing even greater number of layers to support HDI PCB routing for fine-pitched components like BGAs, designers are looking for newer techniques to increase the interconnect density. This is where the ELIC technique comes into use for complex stackup design and HDI routing. The technique is simple to use by extending microvias all through the entire stackup, such that it becomes possible to route signals on high density interconnections between any two layers in the board. This might look to be an extravagant idea, but it has its advantages. However, extending microvias throughout the stackup places constraints on the manufacturing process and the set of materials that fabricators use to build the PCB.

ELIC PCB Stackup Design

Primarily, ELIC replaces through-hole vias in the PCB. However, there is a difference. The initial buildup creates all connections in the board, precluding the use of through-hole drilling. As the ELIC technique makes use of copper-filled structures, building up vias using plating techniques are no longer necessary. IPC warns about extending microvias across the stackup as in ELIC, as it reduces microvia reliability. Therefore, it is recommended to select PCB fabricators with caution, as not many can provide high yield for ELIC boards without there being latent defects in reflow. It may be necessary to implement DFM rules from suitable manufacturers that provide quality ELIC guarantee.

Manufacturing ELIC HDI Boards

For manufacturing ELIC HDI boards, fabricators start with an ultra-thin core that has a solid copper-filled base and laser-drill microvias on it. After filling initial microvias on an inner layer with copper, they add the next dielectric layer in sequential lamination. To build the ELIC PCB stack, each additional new layer undergoes laser drilling, followed by copper-filling for the vias. Repeating this sequence builds up the desired stack with copper-filled microvias.

The structural integrity of the board improves with the sequential copper fill. As long as the fabricator is using strong plating interfaces for the stacked micorvias, the sequential copper fill helps to improve the structural integrity of the board and prevents voiding or dimpling in the inner microvias.


For using ELIC techniques on HDI boards, designers must follow some DFM rules. In addition to following recommendations from the HDI fabrication house, designer must also implement general recommendations like:

  • Selecting an appropriate microvia aspect ratio. This ensures greater reliability in the bare board under fabrication.
  • Specifying filled microvias in internal layers. This ensures there is no dimpling/voiding in the internal layers.
  • Pairing up layer thicknesses carefully with trace width and clearance for impedance-controlled lines. This ensures proper execution of the fanout strategy.
  • Making the layer arrangement symmetric throughout the board.

Applications of ELIC Technology

GPUs and memory cards typically use ELIC technology. Now, newer designs of smartphones, tablets, and wearable devices are also taking advantage of this technology, as most of these devices use components with fine pitch and high pin count. Most of these devices use boards with 10 or more layers. Designers use ELIC in these applications for routing interconnections in these small-footprint boards.

High-speed applications regularly use ELIC technology when they require high Input 0utput density. Instances include use of FPGAs with multiple interfaces to the device. Boards supporting RF routing on PTFE material also use ELIC techniques. In these boards short routes can create impedance mismatch, leading to dominant return loss. Use of stacking microvias helps, as it is possible to route using various layers without requiring backdrilling for stubs. However, designers must limit the useful trace length, as long routes may allow dielectric losses to dominate. Therefore, designers must pay attention when selecting material for HDI boards that will use ELIC technology.

Rigid-flex PCBs are also using ELIC technology. The use of ELIC techniques helps to reduce package sizes in folded rigid-flex boards by judiciously choosing a bend region for preventing redundant stress on microvia stacks. Although designers can apply standard design techniques for flex ribbons as they do for other applications, smaller PCBs can integrate these ribbons if they use ELIC techniques.

ELIC in Rigid-Flex PCBs

Most high-speed, high-density designs have multiple power/ground planes in inner layers to help shield signal layers from each other, thereby reducing crosstalk. This also helps comply with EMC requirements by shielding them from excessive radiation. Designers also use moderate layer count stackups to aid EMC compliance and support high-density fanouts. These boards use creative layout strategies for keeping to a lower number of signal layer counts, while allowing additional grounds, offering a substantial reduction of EMI and crosstalk.


Rush PCB Inc recommends using an advanced PCB CAD package to build an ELIC stackup. Advanced CAD packages have built-in tools that allow easy HDI routing using ELIC techniques.